Tomorrow:Join OpenHW Groups a for S4/E2 of #OpenHWTV! Members from @openhwgroup @AxeleraAI @10xEngineers and @thalesgroup will lead viewers on a journey of the #opensource #RISCV processor CVA6 from Ariane ➡️present. CEO, @FlorianWoh will end the episode with a live Q&A!
📝tinyurl.com/37t9bnuj
.@openhwgroup's next episode of #OpenHWTV introduces the new Chair of the OpenHW Verification Task Group and the expanded charter to support the growing #RISCV verification ecosystem. Register for the live Q&A on Thursday, Oct. 27 at 8 a.m. PT: https://hubs.la/Q01qPk9T0
Original tweet : https://twitter.com/risc_v/status/1585438631120064514
This OpenHW TV episode introduces the new Chair of the OpenHW Verification Task Group and the expanded charter to help support the growing RISC-V Verification Ecosystem. The OpenHW Group welcomes Simon Davidmann of Imperas Software, a founding member of OpenHW, as the new Chair of the OpenHW Verification Task Group (VTG). As part of the CORE-V roadmap, the VTG is updating the successful CORE-VERIF framework to address both the increasing design complexity and improve the DV efficiency for the anticipated bandwidth required for all the new CORE-V cores in development. To address the dual goals of improving and enhancing the OpenHW internal flows for the CORE-V roadmap and help lead the industry adoption of RISC-V, and the associated verification workload, the VTG has started a new methodology project. This episode highlights the new OpenHW VTG Advanced RISC-V Verification Methodology (ARVM) project and outlines the initial concepts and plans for a couple of the sub-projects: • ARVM-FunctionalCoverage: developing open-source VIPs that can be used for many different core configurations/implementations • ARVM-Standards: defining and implementing evolving interface standards (such as RVVI) for test bench components to enable better test bench component reuse and potentially stimulate availability of compatible VIPs --------------- A live Q&A session with today's speakers will follow the video presentation. They include: • Simon Davidmann, Chair of OpenHW Verification Task Group and CEO at Imperas Software • Peter Lewin, Director of CPU Ecosystems at Imagination Technologies • Rupert Baines, Chief Marketing Officer at Codasip • Hosted by Mike Thompson, Director of Engineering, Verification Task Group, at OpenHW Group
RT from OpenHW Group (@openhwgroup)
We'll see you tomorrow morning for our new episode of #OpenHWTV! Travel is covered, but you'll have to provide your own snacks for this road trip.
Register now: https://bit.ly/3bHSR6w
#embeddedworld #opensource #riscv #COREV
Original tweet : https://twitter.com/openhwgroup/status/1562500777381625857
Did you miss out on Embedded World in Nuremburg, Germany in June? This episode of OpenHW TV will give you another chance to view OpenHW Group's live presentation and hear all of the details on the new CORE-V MCU DevKit! OpenHW Group and its members announced one of the industry’s most comprehensive open-source RISC-V Development Kits at Embedded World 2022. The CORE-V MCU DevKit features the OpenHW CORE-V MCU, the CORE-V software developer kit (SDK) with full-featured Eclipse-integrated development environment (IDE) and an open printed circuit board (PCB) design that supports AWS via AWS IoT ExpressLink. The ground-breaking RISC-V-based CORE-V MCU DevKit enables software development for embedded, internet-of-things (IoT), and artificial intelligence (AI)-driven applications. Join Rick O’Connor, President of OpenHW Group, and Richard Barry, Senior Principal Engineer at AWS, for a live Q&A session at the end of the webinar.
RT from OpenHW Group (@openhwgroup)
Join @rickoco President of OpenHW Group, and Richard Barry, Senior Principal Engineer at @awscloud, to learn more about the groundbreaking #opensource #riscv-based CORE-V MCU DevKit during our upcoming #OpenHWTV episode!
To register, please visit: https://bit.ly/3bHSR6w
Original tweet : https://twitter.com/openhwgroup/status/1559934197921357826
Did you miss out on Embedded World in Nuremburg, Germany in June? This episode of OpenHW TV will give you another chance to view OpenHW Group's live presentation and hear all of the details on the new CORE-V MCU DevKit! OpenHW Group and its members announced one of the industry’s most comprehensive open-source RISC-V Development Kits at Embedded World 2022. The CORE-V MCU DevKit features the OpenHW CORE-V MCU, the CORE-V software developer kit (SDK) with full-featured Eclipse-integrated development environment (IDE) and an open printed circuit board (PCB) design that supports AWS via AWS IoT ExpressLink. The ground-breaking RISC-V-based CORE-V MCU DevKit enables software development for embedded, internet-of-things (IoT), and artificial intelligence (AI)-driven applications. Join Rick O’Connor, President of OpenHW Group, and Richard Barry, Senior Principal Engineer at AWS, for a live Q&A session at the end of the webinar.
Join @OpenHWGroup on Thursday, Aug. 25 for the next episode of #OpenHWTV! Attend to learn more about Open HW Group’s ground-breaking RISC-V-based CORE-V MCU DevKit that enables software development for embedded, #IoT and AI-driven applications: https://hubs.la/Q01jHM080
Original tweet : https://twitter.com/risc_v/status/1557472854639345664
Did you miss out on Embedded World in Nuremburg, Germany in June? This episode of OpenHW TV will give you another chance to view OpenHW Group's live presentation and hear all of the details on the new CORE-V MCU DevKit! OpenHW Group and its members announced one of the industry’s most comprehensive open-source RISC-V Development Kits at Embedded World 2022. The CORE-V MCU DevKit features the OpenHW CORE-V MCU, the CORE-V software developer kit (SDK) with full-featured Eclipse-integrated development environment (IDE) and an open printed circuit board (PCB) design that supports AWS via AWS IoT ExpressLink. The ground-breaking RISC-V-based CORE-V MCU DevKit enables software development for embedded, internet-of-things (IoT), and artificial intelligence (AI)-driven applications. Join Rick O’Connor, President of OpenHW Group, and Richard Barry, Senior Principal Engineer at AWS, for a live Q&A session at the end of the webinar.
Register for the next #OpenHWTV episode on verification of the CORE-V-MCU with @OpenHWGroup, @QuickLogic_Corp & Datum Technology Corporation on Thursday, May 26 at 8 a.m. PT. https://hubs.la/Q01bNzv90
Original tweet : https://twitter.com/risc_v/status/1528799204692344834
This episode of OpenHW TV will focus on the verification of the CORE-V-MCU currently under development by the OpenHW Group. Followers of OpenHW TV may recall that the CORE-V-MCU started out its life as the Arnold device (https://bit.ly/3PrfMCb) from the PULP-Platform team at ETH Zürich. Arnold has been successfully implemented in silicon, so a reasonable question is: “Why does the CORE-V-MCU need more verification?" The answer to this question lies in the goals of the CORE-V-MCU which are to enable rapid deployment of hardware and software development kits and to accelerate the design of commercial SoC devices based on CV32E40P. Enabling hardware and software dev-kits calls for an accelerated development cycle that puts an SoC (ASIC) implementation of CORE-V-MCU into developers hands as soon as possible. To support this goal, a verification project that employs processor-driven testing is being used. This has enabled rapid deployment of a set of simple C test-programs called “cli-test”, running under FreeRTOS. To support developers of commercial grade SoC devices requires the same level of verification that has previously been deployed on the CV32E40P core. The CORE-V-MCU-VERIF project aims to deploy a complete UVM verification environment that is capable of fully verifying the MCU as well as future commercial SoC devices based on CV32E4 cores. This presentation will be led by: Mike Thompson, OpenHW Group Director of Engineering, Verification Task Group Tim Saxe, CTO of QuickLogic David Poulin, President of Datum Technology Corporation Mike will (briefly) re-introduce the CORE-V-MCU before handing the discussion over to Tim, who will summarize the goals of the first SoC device based on the CORE-V-MCU, and David, who will introduce a project to fully verify CORE-V-MCU with an "industrial grade" UVM verification environment.
Registration is open for the next episode of #OpenHWTV! The episode will focus on verification strategies for the CORE-V-MCU, which is under development by the @OpenHWGroup. Register here: https://hubs.la/Q01bB0rq0
Original tweet : https://twitter.com/risc_v/status/1526986550998876164
This episode of OpenHW TV will focus on the verification of the CORE-V-MCU currently under development by the OpenHW Group. Followers of OpenHW TV may recall that the CORE-V-MCU started out its life as the Arnold device (https://bit.ly/3PrfMCb) from the PULP-Platform team at ETH Zürich. Arnold has been successfully implemented in silicon, so a reasonable question is: “Why does the CORE-V-MCU need more verification?" The answer to this question lies in the goals of the CORE-V-MCU which are to enable rapid deployment of hardware and software development kits and to accelerate the design of commercial SoC devices based on CV32E40P. Enabling hardware and software dev-kits calls for an accelerated development cycle that puts an SoC (ASIC) implementation of CORE-V-MCU into developers hands as soon as possible. To support this goal, a verification project that employs processor-driven testing is being used. This has enabled rapid deployment of a set of simple C test-programs called “cli-test”, running under FreeRTOS. To support developers of commercial grade SoC devices requires the same level of verification that has previously been deployed on the CV32E40P core. The CORE-V-MCU-VERIF project aims to deploy a complete UVM verification environment that is capable of fully verifying the MCU as well as future commercial SoC devices based on CV32E4 cores. This presentation will be led by: Mike Thompson, OpenHW Group Director of Engineering, Verification Task Group Tim Saxe, CTO of QuickLogic David Poulin, President of Datum Technology Corporation Mike will (briefly) re-introduce the CORE-V-MCU before handing the discussion over to Tim, who will summarize the goals of the first SoC device based on the CORE-V-MCU, and David, who will introduce a project to fully verify CORE-V-MCU with an "industrial grade" UVM verification environment.
Florian - RISC-V Ambassador
RISC-V