πΊπ¦ haxadecimal π«πI'm working on a design for a high-efficiency instruction decoder for a new #Z80 core design. Apparently the world doesn't have enough open-source Z80 core designs yet.
I'm trying to make this core much more cycle-efficient than normal Z80 cores, or even eZ80 cores. A normal Z80 core takes 4 clock cycles for the simplest instructions. I'm trying to get those down to 1 clock. I'm using a synchronous memory bus, and a loosely coupled instruction prefetch and decode unit.
#FPGA #CPUCoreDesign
I'm trying to make this core much more cycle-efficient than normal Z80 cores, or even eZ80 cores. A normal Z80 core takes 4 clock cycles for the simplest instructions. I'm trying to get those down to 1 clock. I'm using a synchronous memory bus, and a loosely coupled instruction prefetch and decode unit.
#FPGA #CPUCoreDesign