Mastodawn

NeGate Jan 25, 2025

@regehr My current plan for accommodating for C's... inadequacies is to write DSLs for machine description stuff, I've got a promising little pattern matcher working recently on a dev branch. Rust's ownership spooks me a bit when it comes to mutable graphs and GCs are pretty nice and convenient but i effectively emulate that with my arenas doing copy compacting

NeGate Jan 25, 2025

@regehr Yea, it'll take a while before it's seriously competing but I do think it's not only possible but achievable by me (and others).

NeGate May 21, 2024

I'm so many layers into this dev branch I gotta start unwinding my stack, basically just missing:
* Bug fixes
* Finish new builder API
* Bug fixes
* Bug fixes
* Write MIPS tutorial
* :(

What I did:
* Made it easier to describe RA constraints
* Machine SoN
* Optimizer improvements (Loop rotation and tons of peeps)
* Lots of random things

Show thread

NeGate Feb 22, 2024

@pervognsen So I made SCCs from my call graph and was gonna steal the bottom-up stuff from LLVM, inlining until it's a certain size might be a decent metric to start. Profiling counters would be helpful tho

NeGate Feb 22, 2024

I made an inliner but with no heuristic, i'm a man with no purpose, or a dog with no dog purpose 😔. Yea it just copies graphs but idk where to start on good heuristics, considering a simple node count to start.

NeGate Feb 17, 2024

@regehr "real recognize real"

Show thread

NeGate Jan 10, 2024

@10aded So the different order is because my code is actually in sea of nodes form, i merely flatten it to display in this pretty printer which means there's not really a total order for instructions in basic blocks (there's not even basic blocks lol). v33 and v35 most likely don't show up in the numbers because they were the "fib" symbols which are folded for pretty printing purposes.

Show thread

NeGate Dec 4, 2023

@pervognsen Here's a stupid thing i ran into writing a C parser:

int a = sizeof(int) { 0 };

Show thread

NeGate Dec 1, 2023

@190n Because they needed to pack things so they special cased RBP such that, the encoding for RBP indirect is RIP-relative and real RBP indirect is RBP indirect with a 0 displacement

NeGate Nov 25, 2023

Started a few days ago to rewrite my codegen stuff to be more general so I can add more targets quickly, i've gotten x64 to somewhat work again (not complete but enough to prove it's a good design)... Now it's finally time, Aarch64. BTW for anyone who's done ARM work, why does MSVC try to allocate x8 over x0 when given the choice, I dont think it was preserving it for something maybe it's some hardware preference thing?