@vitaut What a chilling idea.

@vitaut See the issue is that adding safety to C++ requires practicing self reflection.

@harold Thanks for the heads up. I've fixed it now. I did indeed intend for it to be (value ^ mask) - mask. I wasn't aware that I was on your radar. I appreciate you taking the time to spare my work some attention.

@compfu That does appear to be the case. The image isn't quite as readable as a still but the animation can be seen here: https://www.artstation.com/artwork/L4Gk30

@jannem I believe they're talking about MULX being suspected of causing hardware degredation under heavy workloads. https://www.theregister.com/2025/08/29/amd_ryzen_twice_fails_in/

@vitaut They're reaping/harvesting souls, not just cutting them down, so it should really be a combine harvester.

@wolf480pl You might be thinking of zeroing idioms, instructions that clear a register's contents but which are never scheduled, instead being handled with by a direct update to the register alias table. However, they involve no special instruction encoding. From the reference image, we can see that if you increment the destination register (whatever width it may be), the encoding's trailing byte is simply incremented in turn, with the self XOR cases not breaking the pattern.