Excited to announce that Joseph Rogers' Nescope paper has been selected as an IEEE Micro Top Pick. The full paper is here: https://dl.acm.org/doi/full/10.1145/3695053.3731014

To me, the key contribution of this paper is that it provides a way to reason about how changes to a system's workload -- which we call workload churn -- impact key performance metrics over the lifetime of a System-on-Chip (SoC). This capability creates a lot of possibilities for future research at @CAL_NTNU, @sfi_nice, and other labs.

The Norwegian Center for Intelligent Computers and Electronics (NICE) invites applications for a PhD candidate in computer architecture, focusing on designing efficient Edge AI accelerators.

https://www.jobbnorge.no/en/available-jobs/job/297610/phd-candidate-in-edge-ai-accelerator-design

Most entries in a Branch Target Buffer share their tag with other entries. So why are we storing it over and over again?

I am happy to announce that Rakesh Kumar’s and my paper "Driving the Core Frontend With LiteBTB" was accepted to IEEE Computer Architecture Letters. In it, we explore how tag redundancy in BTBs can be systematically exploited to reduce storage overhead without sacrificing performance.

https://ieeexplore.ieee.org/document/11391652

@CAL_NTNU

BTB tags are now the dominant storage cost in modern BTB designs – and nobody has studied them carefully. Until now.

I am proud to announce that our paper, "Understanding BTB Tag Sizing," has been accepted to ISPASS'26!

@CAL_NTNU

Just announced two PhD positions relevant to @sfi_nice. One focuses on modeling Edge AI architectures, and the other one is about enabling dependency-aware performance analysis.

More information is available in the complete job announcements:
- Edge AI modeling: https://www.jobbnorge.no/en/available-jobs/job/295625/phd-candidate-in-modeling-edge-ai-computer-architectures
- Dependency-aware performance analysis: https://www.jobbnorge.no/en/available-jobs/job/295310/phd-candidate-in-computer-architecture-focusing-on-dependency-aware-performance-analysis

Håvard Krogstie's first paper received the distinguished paper award at CGO 2026 in Sydney.

PIP is the first points-to analysis that's both sound and practical for incomplete C programs.

If you want to read the paper, then you can access it here http://www.sjalander.com/research/pdf/sjalander-cgo2026-pip.pdf

I will give an invited talk about our dynamic-HLS work at the Workshop on Co-evolution of Algorithms, Compilers, and Hardware for Performance.

https://fastcode.org/events/coevolution-workshop/

Amund Bergland Kvalsvik did an excellent job at defending his PhD thesis titled “Haunt Me No Longer! Finding Meaningful Solutions to Speculative Side-Channel Attacks”.

The work has resulted in one ISCA and two MICRO publications, which are the two most prestigious conferences in computer architecture.

As a proud supervisor, I'm looking forward to following Amund's continued career and future achievements.

https://hdl.handle.net/11250/5319646

I am excited to announce that our paper was accepted to CGO 2026!

We show how points-to analysis of C programs can be performed, even if you only have access to parts of the program. Using the C memory model, we can reason about pointers with unknown origins, and conservatively handle statements in the rest of the program. We introduce techniques to keep the representation efficient, and providing more information than existing local analyses.

URL: https://arxiv.org/abs/2512.07299
@CAL_NTNU @EECS_NTNU