For anyone playing along at home, the SiFive E300 uC image running on an Arty FPGA can be interfaced with a JLink Segger JTAG device, rather than an Olimex ARM JTAG adapter.

The only adjustment is don't connect pin #2 as it's N/C on the JLink.

Then, in openocd, you can just comment out all the FTDI interface details and replace it with a single line:
interface jlink

Easy breezy. #RISC-V