Nice to see my white 6502 CPU is OK, and is indeed missing the ROR instruction.
@hansotten Here's a workaround for missing ROR A by the way (8 bytes, up to 8 cycles):
BCS set
LSR A
BPL done ; always
set:
LSR A
ORA #$80
done:
Eight ROL A instructions will also do the job in the same number of bytes but twice as slow.
Source: https://www.pagetable.com/?p=406#comment-2037
