Bryan Steele Mar 31

Theo de Raadt has introduced a new hw.blockcpu sysctl to #OpenBSD -current to offer more control over which CPU core types (Performance, Efficiency, and SMT) are available to schedule processes on. Modern Intel (and ARM) CPUs additionally have slower LP-E (low-power) cores that severely hinder system performance.

deraadt@ modified src/sys/*: Some new intel machines have a new 3rd tier of cpus called LP-E which are E-core (Atom) without L3 cache. These cpus are Lethargic, and it sucks when processes migrate to them.
This introduces sysctl hw.blockcpu= which takes a sequence of 4 letters.
S (for SMT), P (regular performance cpu), E (efficient cpu) generally 80% to 50% as fast), and L (lethargic cpu) which are even slower.
By setting this, you can select cpus to kick out of the scheduler. The default is SL.
The hw.smt sysctl remains for now but we will eventually delete it.
hw.smt changes and follows hw.blockcpu=S.
ok kettenis mlarkin

Show threadBryan Steele 

Mark Kettenis has added #OpenBSD/arm64 support for the new hw.blockcpu sysctl, classifying CPU types based on device-tree and ACPI CPPC information.

kettenis@ modified src/sys/arch/arm64/*: Add hw.blockcpu support for arm64. Here we classify CPU cores based on their "capacity". This a concept borrowed from the device tree standard that indicates the nominal performance of a CPU core. For ACPI machines we use similar information from ACPI's Collaborative Processor Performance Control (CPPC). If performance is less than 30% of the fastest cores in the same we classify them as L. Between 30% and 80% we classify them as E.
And above 80% we classify them as P. The CPU capacity is communicated to userland though kstat(4).

ok deraadt@, jca@

In addition to using kstat(1) on your machines, kettenis@ tested the following machines:

  • Lenovo x13s (Snapdragon 8c): Cortex-A78C -> E + Cortex-X1C -> P
  • Rock 5B (Rockchip RK3588): Cortex-A55 -> E + Cortex-A76 -> P
  • Apple Mac mini (M2 Pro): Blizzard -> E + Avalanche -> P
  • Radxa Orion O6 (Cix CD8180): Cortex-A520 -> L + Cortex-A720 -> P
Apr 3 at 9:27pmWeb