Mastodawn

Got a few Samsung K4RAH165VB DDR5 1Gx16 chips from Aliexpress to include as an option on the Wren phase noise analyzer. It will work without that populated. Expensive and hard to find currently. Was $8 per chip on LCSC not long ago.

It has a few advantages over DDR4. CA bus terminations are built in, CA is POD IO eliminating a bunch of parts, termination supply. Fewer pins, cleaner layout, single HPIO bank, 2 signal layers to route.

I need to get back on the DDR5 controller for Ultrascale+.

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Darrell Harmon

The DRAM area is 3 ground planes, 1 power plane, 2 signal layers which also has room for the VPP plane so easy 6 layer layout with all the noisy signals on inners.

Officially, this is all datasheet compliant at 2100 MT/s. Unofficially, I expect it to work at 2933 MT/s with the FPGA slightly overclocked. DDR5 supports 2000-2100 MT/s, 2933+ MT/s, nothing in between.