✧✦Catherine✦✧to paraphrase that one veterinary handbook; if you need to get a Linux SoC to work:
HP van Braam@whitequark if performance isn't the highest priority some fpga with a LiteX SoC is an option!
If you're happy with ~120MHz RiscV (but potentially multiple cores?) you can even do it all with an OSS toolchain.
Is it a great solution? No! But it does solve some of the problems.
@hp yeah, I've been working on OSS FPGA toolchains (and Migen, in the past) for almost a decade now...
@whitequark sorry! I didn't know!
Migen is great! I've been using it for the past few weeks. Thanks for your work! ♥️
@hp I actually think it's terribly designed and implemented, so much so I at one point designed its replacement (which is now called Amaranth)
@whitequark I'll check it out! I've been enjoying migen in the context of LiteX and not having to write system verilog. 😅
The abstractions like SDFTristate and such is really nice to keep my cores portable before I settle on the the final FPGA. Currently my stuff works ok on an xc7 and an ECP5.
I was quite impressed.
@hp Migen is generally an improvement on Verilog as long as you don't look too closely at what it's really doing, but it's really buggy (look at every bug I've filed with a
fixed-in-nmigen tag) and there are no attempts to nail down a semantic aside from "well, this translates to such and such Verilog"; there's also a bunch of really annoying limitations like "everything goes into one module", "Record is trying to do two things and does three of them poorly", and "no async resets"@whitequark sound like I'll probably be less impressed when I use it more then? 😅
I could wrap something written in your new system and use it with LiteX I think? I'll try porting a small core I wrote!
Thanks for the information!
@hp yes; particularly if you want to know exactly what behavior is guaranteed (this applies to LiteX even more so than Migen, we spent a lot of effort on streams for example and LiteX's ones are... inconsistent)
yes, you can use Amaranth and LiteX together, but you have to combine them at the Verilog/RTLIL level, they don't directly interoperate
@whitequark Thanks for the explanation!
Given that LiteX already has a Zephyr port moving everything over might be a challenge. But I think integrating at the Verilog level should be fine.
I'll give it a whirl! My custom peripheral is only ~1k lines of migen so it shouldn't be very hard to port.