#lazyweb Is it correct to say that the 68000 and 68008 only have atomic load/stores of 16-bit and 8-bits respectively*?
* Unlike most CPUs, an interrupt will pause the current instruction and continue from where it left off. But I haven't read the patent or RE'd microcode. So not clear to me if 68000 will wait to honor an interrupt until after an up-to-32-bit load/store completes.
@dalias This is correct for most CPUs; the 68k saves enough of its internal state to the stack on interrupt to continue in the middle of an instruction. It's in the patent, supposedly*.
* Which, I did not read, and I've heard conflicting info over the years as to whether the patent correctly describes all the saved state.
@dalias I could do the same thing with Sentinel. I would have to constantly check for interrupts each microinstruction (3-way or n-way jump in many cases), and if found, divert to a routine to save the microprogram counter to the stack, and a few other state bits.
It would help with interrupt latency in Sentinel a bit, but the extra hardware and microprogram required is Not Worth The Savings.
Also, I don't think RISC-V allows you to use the stack as a private data :D.
William D. Jones
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