Per Vognsen7h ago
I spent some time looking at GBA stuff after posting about it a few days ago. It's been so long since I've touched ARM32 that I'd forgotten the insane shit you can do in one instruction, e.g. LDMEQFD SP!, {R0, R2-R5, PC}.
Show threadNick Ludlam7h ago
@pervognsen Is that still technically RISC? Or has RISC just shifted its baseline because of how execution architecture has matured?
Show threadPer Vognsen7h ago
@nick I'm pretty sure that LDM would have worked as-is with the original ARM1 instruction set so this was there in the beginning. ARM has never been RISC in any meaningful sense. It's a load/store architecture with a bunch of GPRs but that's about it. I guess if you wanted to be snide, you could say that it shares in the earliest RISC tradition of shipping parts of your microarchitecture as the ISA (barrel shifter, predication, etc) like MIPS did with branch delay slots and imprecise exceptions.
Show threadOwen Anderson7h ago
@pervognsen @nick ARM64 at least has fixed-size instructions.
Show threadOwen Anderson7h ago
@pervognsen @nick Classic ARM32 does as well, but then Thumb had to come along and screw everything up.
Show threadPer Vognsen7h ago
@resistor @nick Speaking of GBA, I'm pretty sure Thumb came out of early design discussions between ARM and Nintendo, years ago before the GBA was actually designed. I assume a lot of ARM's subsequent success in embedded was contingent on that.
Show threadJosh Simmons
@pervognsen @resistor @nick do you know if titles used thumb much in EWRAM on the gba?
11:21pmPhanpy
Show threadPer Vognsen6h ago
@dotstdy @resistor @nick I think almost exclusively if they knew what they were doing since otherwise you need 2 bus cycles just to fetch an instruction. If you wanted to use 32-bit instructions you'd put that code in an IWRAM section.