chaseadam1d ago
bunnie

One of my favorite features of the Baochip-1x is the BIO. It's an I/O coprocessor that is based on the PicoRV32, with custom register extensions to allow direct access to GPIOs from the ISA.

Read more about the BIO at this blog post: https://www.bunniestudios.com/blog/2026/bio-the-bao-i-o-coprocessor/ I go in-depth into the architecture and its trade-offs relative to the PIO, and conclude by working through a couple of coding examples.

Mar 20 at 4:48pmWeb
Show threadwaldi1d ago

@bunnie Thank you for another data point why all hardware for the last decades also include "general" purpose cpus. it is just always smaller in terms of chip size.

(Related to the FSF stance that firmware in flash is good, firmware loaded from the host os is bad.)

Show threadLuke Wren1d ago
@bunnie This is a really elegant design. PIO was definitely warped by too much emphasis on single-cycle operation at low fmax, and the assumption that you always have a nearby (specifically bus-synchronous) CPU to poke and prod it. This makes much more sense for your system and choice of frequency ratio.
Show threadbunnie1d ago
@wren6991 thanks! I also really enjoyed analyzing and understanding the PIO, it's a really interesting point in the design space and there's a lot of clever ideas in there.
Show threadchrysn1d ago

@bunnie Cool design and post, many thanks!

How do quantums/events work out when protocols mix event sources, eg. in Manchester codes where we jump between "read after fixed time" and "wait for edge to restart timer", or when waiting for either an edge or a time (eg. timouts)? Would those always use two BIO blocks at faster rates (like 5Mbd)?

If so, could future baochips have more of them, like, 8?

For example, IIUC, mixing two S/PDIF inputs into one would need at least 5 blocks.

Show threadbunnie19h ago
@chrysn You can do both modes, you can always read an I/O pin and poll its state without relying on the quantum mechanism. At 5 Mbaud I would guess you can do polling OK.
Show threadBrian Swetland1d ago
@bunnie I really like using the top half of the register file for block-specific functionality, which ends up being doubly clever due to RV32E already defining a standardized ABI using only the bottom half (if you're going to re-use existing higher level tool chains, etc). Nice design.
Show threadWolf480pl1d ago
@bunnie
reminds me of TIS-100
Show threadMike Bell3h ago

@bunnie BIO looks really interesting, and having a full RISC-V core in a DMA engine could be very handy. I’ve tried to use PIO for data stream manipulation but it’s not particularly suited for that. And 4kB program memory for each core is also a massive luxury!

It’s a shame that PicoRV is 3 CPI though, means that even though the clock is faster this likely ends up net slower than PIO on the RP2 for most things. Maybe a slightly higher throughput core (with the B extension too?) could tilt the balance without getting bigger than PIO?