allisonfuriously clicking through the histories of various microprocessors on wikipedia so i can figure out who to blame for the fact that you can't push/pop a single byte to the stack on the gameboy in an atomic fashion (you can only push/pop register pairs). a fact that led to a stupid bug that took me two days to figure out
(as far as i can tell, the gameboy's SM83 has it because the Z80 has it, and the Z80 has it because the Intel 8080 has it, but I can't figure out what the Intel engineers were thinking when they decided this is how it would work on the 8080. Stanley Mazor wrote about the design process of the 8080 here https://ieeexplore.ieee.org/document/4287219 but on the topic of push and pop he only says "Push and Pop instructions were needed for each of the three register pairs.")
@haitchfiveI think it was just a practical convention inherited from those who came before them at IBM and other places.
From the perspective of business machines, it would rarely make sense to push data that's not word-sized data.
Which is still the same rationale ARM, Intel, AMD follow to date.
But you can still do
DI
DEC SP
LD (SP), A
EI
For most intents and purposes indistinct from a theoretical PUSH A
@haitchfive alas the gameboy doesn't let you load directly to SP—you either have to go through HL (LD SP, HL or LD HL, SP+n) or use the PUSH/POP instructions and adjust the stack pointer after with INC SP/DEC SP. (which leads to the problem I encountered: if an interrupt occurs between the POP and the DEC SP, a byte on the stack gets overwritten by the interrupt handler pushing the return address!)
@aparrish Ahhh I see, I didn't know that was unavailable on the SM83, I assumed perfect backwards compatibility.
Can you disable and enable interrupts though, to guard the unsafe parts of the atomic operation?
David JONES@haitchfive @aparrish backwards compatibility with what? The Z80 doesn't have _any_ LD instructions that use (SP); PUSH and POP are, on the Z80, the only way to indirect via SP. (and, FWIW, the only way to "read" SP is to store it in memory: LD SP, (NN) ).
Compatibility in the sense of supporting the specific snippet I posted earlier.
DI
DEC SP
LD (SP), A
EI
@haitchfive but i don't understand what CPU you think can run that snippet, the Z80 cannot.
@drj Sorry, something more like
DI
EXX
DEC SP
LD HL, 0
ADD HL, SP
LD (HL), A
EXX
EI
I wasn't implying I could deliver a complete Z80 solution on social media, but here we are
@haitchfive Oh yeah, ADD HL, SP i had forgotten about that.