Wilson J. HolmesMar 17
✧✦Catherine✦✧

i think i've discovered something really ironic

so, SPI NOR flash standardization is awful. every vendor does literally whatever they want at all times and then JEDEC comes a year or two later, writes it down, and host controllers have to deal with it

SPI NAND flash does not have such a "standards" body. there is self-description data but it's just the ONFI NAND stuff describing geometry, with no references to the command set.

as a result, vendors (seemingly) are under pressure to actually be compatible with each other, and the instruction set is quite interchangeable between devices. perhaps not completely (i haven't mapped enough of them yet), but to a much greater extent than SPI NOR flash

Mar 17 at 12:04amWeb
Show threadTóth Gábor BaltazárMar 17

@whitequark
why is there such a difference between nand and nor?

it shouldn't even be visible to the other device what technology it is, no?

Show thread✧✦Catherine✦✧Mar 17
@tthbaltazar no, you have to treat NAND and NOR very differently (NOR doesn't need bad block management for example, NAND does. this is just the most glaring difference, there are dozens more)
Show threadjn (big endian energy)Mar 17
@tthbaltazar @whitequark i think the reason is that NAND flash is unreliable enough to require ECC and remapping, whereas with NOR flash you can get away with storing data byte-for-byte and wherever you want
Show threadAndresMar 17
@whitequark the only differences i found between nands are how to change to slc mode(one has a setfeature flag, and other has a prefix command for every data/address command) and also that nands with pages of 16KB have different addressing (one byte more).
Show thread✧✦Catherine✦✧Mar 17
@andydemski oh god. is ONFI data at least sufficient to determine the addressing bytes unambiguously?
Show threadAndresMar 17
@whitequark i'm not sure. I think it depends on memory layout but i will check.
Show thread✧✦Catherine✦✧Mar 17
@andydemski thank you!