@whitequark this is cursed beyond belief, w-why?!

@k i've compiled the entire FPGA toolchain (synthesis and P&R) to WebAssembly, and most of the verification options (whether Verilator or CXXRTL) output C++. so you need to be able to compile C++ code to simulate RTL

@whitequark I don't usually follow people from mastodon social because the instance is unmoderated but you've just earned it, holy hell.