The main problem with BSRAM initialisation is not placing the bits in the right place (this is easily detected after a couple of comparisons of compiled black-and-white images as data for BSRAM), but correctly calculating the CRC.
The img shows the streams after #Apicula and after IDE. The two CRC bytes before the long sequence 1 do not match. This means that I either did not take something into account, took something extra, or did not initialise the the CRC calculation correctly🤪
#fpga#gowin