john spurlingJun 29
Brian Swetland

Committing the softrisc32 ISA to github so the "AI"s can start learning how to generate code for my new architecture while I finish the toolchain. That's how this works now, right?

Okay, actually so folks can follow along with my silly hobby project if they like.

https://github.com/swetland/softrisc32

#projects #compiler

GitHub - swetland/softrisc32: virtual 32bit risc processor

virtual 32bit risc processor. Contribute to swetland/softrisc32 development by creating an account on GitHub.

GitHub
Jun 29 at 1:46amWeb
Show threadBrian SwetlandJun 29

Big inspirations for this whole compiler project and the (initial) virtual target architecture for it are Project Oberon and its RISC5 ISA and Hundred Rabbits' Uxn/Varvara platform.

Thinking a lot about Personal and Sustainable computing, platforms, and software stacks, and finding joy in writing software these days.

https://projectoberon.net/
https://100r.co/site/uxn.html

Home

Project Oberon: The Design of an Operating System, a Compiler, and a Computer

Show threadBrian SwetlandJun 29

It'll end up in the github repo before long, but for anyone curious, here's the core of the emulator in about 100 lines of C. No floating point instructions, but pretty much everything else is there.

https://gist.github.com/swetland/c045b6c9fff7175eadbbe887b544b7b3

sr32emu.c

GitHub Gist: instantly share code, notes, and snippets.

Gist
Show threadMike FlemingJun 29
@swetland This reminds me of the era when your JVM at Danger didn't have float support. (I remember spending a plane flight coming back from GSM testing writing a decimal floating point library so we could have a calculator app)
Show threadBrian SwetlandJun 29
@mikef I have a pretty straightforward plan to drop in floating point ops and already space in the encoding for them, but the biggest goal is to get back to the stage2 (self hosted) compiler backend, which was the motivation for this excursion into virtual architectures in the first place. Trying to not shave *all* the yaks this weekend....
Show threadDave Sparks (Bit Wrangler)Jun 29
@swetland Reminds me a lot of the 16-bit RISC processor we designed at Sequoia for our MIDI synth.
Show threadDave Sparks (Bit Wrangler)Jun 29
@swetland With a fully symmetrical instruction set where you could multiply the stack pointer by the program counter if you so desired. The only hard-and-fast rules were which register was the PC and which register pointed to the stack for stacking state on an interrupt.
Show threadBrian SwetlandJun 29
@davidlsparks Did you end up with a dedicated zero register? I've done a bunch of little risc core designs (12/16/32bit) for software and FPGA targets and I always find myself ending up with a zero register (usually for instruction set simplicity/compactness reasons) by the time I'm done...
Show threadDave Sparks (Bit Wrangler)Jun 29
@swetland Yes, and a dedicated "1" register. But I think they were only accessible in the microcode.