Mastodawn

Zebra North Jan 26, 2025

This is probably the best modern writeup on decoupling capacitance that I've seen. It's clear and brings the receipts!

https://codeinsecurity.wordpress.com/2025/01/25/proper-decoupling-practices-and-why-you-should-leave-100nf-behind/

My EE colleagues at Oxide (who are much better at this than I am) have been trying to drive this point into my head for years.

In related news, I just last week made my first board that was unstable at full CPU speed until I swapped out the 100nF "habit cap" for a 1u. It's real!

Proper decoupling practices, and why you should leave 100nF behind

Ever wondered why 100nF is a go-to value for decoupling capacitors? This number has pervaded in datasheets and electronics advice going back to the 1980s, and is still widely present in the datashe…

codeinsecurity

Jeff Miller (orange hatband)Jan 26, 2025

@cliffle I enjoyed reading the decoupling capacitance article because of how easy it was to follow.

No beverage or lengthy read needed, and the story was carried by a few graphs and notes about the digital switching speed changes since the 10pf rule for decoupling capacitors gained currency.

Graham Sutherland / Polynomial Jan 26, 2025

@cliffle glad you enjoyed it! :)

Jonathan ‘theJPster’ Pallant Jan 26, 2025

@cliffle I don’t really know what I’m doing but friends convinced me to just use 0603 10uF as a standard decoupling cap on my Neotron Pico board.

cliffle Jan 26, 2025

@thejpster Just be careful how many of them you use, you could wind up with kind of a lot of bulk capacitance on the rail if you have several 10uF caps around. That can lead to bonus behavior both on startup (e.g. damaging a regulator due to very high inrush current) and shutdown (e.g. leakage keeps CPU from completely resetting)

Jonathan ‘theJPster’ Pallant Jan 26, 2025

@cliffle I counted and there's about 14 on the 3.3V rail, plus a big-ass 100uF cap for the audio codec. But good to note, thanks.

cliffle Jan 26, 2025

@thejpster that's a lot -- what's your 3.3V rise time look like? You might be stressing the 3.3V regulator at startup (unless it's some fancy DCDC or PMIC with a constant-current mode)

Jonathan ‘theJPster’ Pallant Jan 26, 2025

@cliffle it’s an AMS1117. Nothing fancy. I should dig out a scope and look at it I guess.

jannic Jan 26, 2025

@thejpster @cliffle This split, piecewise linear slope doesn't look like the result of too much capacitance?!
Measured on J1303, I should check the schematics if that's the right power rail. I just took the first pin labeled "3.3".

jannic Jan 26, 2025

@thejpster @cliffle I added a trace for the 5V rail, and it looks like 3V3 starts rising first. How can that even be? The AMS1117 regulator is powered by that 5V supply. Jonathan, does the BMC turn on something else that could somehow back-power the 3V3 line from auxiliary power?

cliffle Jan 26, 2025

@jannic @thejpster am I reading the screen right and your X axis division is 500µs? A 1.5ms rise time for 3.3V against 240µF capacitance would be about 520 mA, so while that's nothing to sneeze at, it's not going to pop your regulator.

jannic Jan 26, 2025

@thejpster @cliffle It's indeed backpowering the 3V3 line from 3.3VP through the MCP23S17 I/O expander. Verified by removing that chip from its socket. Now the rising edges look much more sensible. Removing only the RP Pico didn't change the slopes.

While the schematics have a comment "Lines to host are hi-Z until host is powered (i.e. 5V and 3.3V look good) to avoid back-powering.", the BMC source code contains this comment in the power-up handler: "TODO: Start monitoring 3.3V and 5.0V rails here". This explains a lot.

This would mean about 45mA running through that chip, which might be a bit too much: The datasheet lists maximum clamp currents (V_I > V_DD or V_O > V_DD) of 20mA.

Jonathan ‘theJPster’ Pallant Jan 27, 2025

@jannic @cliffle yeah I should get around to fixing that. Having one chip running whilst the rest of the board is powered down is a bit of a software nightmare. At the very least we could delay turning on all the GPIO outputs after a Power On button press. PRs welcome!

Oliver Gerlach Jan 26, 2025

@cliffle Thanks so much for sharing this. When I learned and seriously thought about decoupling, the 100n + 1u combo was totally reasonable. From then on I went with it, because "it just worked" . Never put much thought into it until today.

root42 Jan 26, 2025

@cliffle ...or: just stick with C64s and other 6502 based computers. Then 100nF are just fine. :-D

cliffle Jan 26, 2025

@root42 they're probably not; one of the points the article is making is that capacitors have improved dramatically, and you may not be able to get a 100nF with the same bad specs anymore.