Alphane MoonOnly about 720,000 Qualcomm Snapdragon X laptops sold since launch — under 0.008% of the total number of PCs shipped over the period, or less than 1 out of every 125 devices
pycoraxWith Lunar Lake proving that x86 can contend with ARM if it wants to, I’m not sure why anyone would consider these laptops which perform about the same but with compatibility issues.
Power efficiency. Arm promises the same performance at lower temps and wattage than x86 at competitive price points. That’s a really attractive proposition for the laptop market. x86 can be as small format, as power efficient, as cheap, or as powerful than ARM but not all at the same time.
That’s not true at all. It’s a common misconception but there’s nothing stopping x86 from also targeting a power efficient design. It’s all about architecture and not the instruction set. There just hasn’t been an incentive for Intel and AMD to focus their architectures on power efficiency since they make much more money in the server space. Lunar Lake is Intel’s first real attempt at it.
The Z1 Extreme has already shown very comparable and sometimes better performance and power efficiency as the M2 chips and the Lunar Lake chips trade blows with the X Elite not just in performance but also power draw.
If you wanna know more, this goes very in depth on what the differences are: chipsandcheese.com/p/why-x86-doesnt-need-to-die
ඞmirOne of the reasons why it’s harder for x86 is because the instruction set is simply more complex. You either need a decoder to turn it into simpler instructions, or more hardware to handle the complex instructions, both of which increase the number of transitors, and therefore power draw until we create a room temp superconductor
Both RISC and CISC decode into micro-ops regardless. Read the article, it goes into detail, the diagrams make it pretty clear if you don’t want to read the whole article. Modern processors have no notable differences between RISC or CISC designs anymore in the way you described. The only thing RISC and CISC differs in is essentially just the interface that assemblers assemble code into. Which is different across ISAs anyways.
Thanks for taking the time to correct me. I shouldn’t rely on elementary knowledge from a BSc that discussed chips from 3 decades ago.