intel should have only made five condition codes then the physical register file entries would be 69 bits and at hayley @h ayleypatton @halley would be much happer
@moonchild is there a condition code per physical register

also congrats you are third to misspell it as Halley (I was first but I did it backwards)

@hayley yes you have to rename condition codes and most of the time they’re generated by an arithmetic op so you just store them in the same physical register as the arithmetic result

i was going to say ‘haly’ but it seemed disrespectful

@moonchild thankyou moon child very cool
@moonchild idea: stick the SPAZO group on the register, but keep C separate (it's already renamed separately)
@harold lol why's it renamed separately

@moonchild because of inc/dec

so OK it's not *always* renamed separately, but on the CPUs that don't do it, inc/dec kinda suck

@harold oh is htere nothing else except inc/dec wrt c that preserves flags? should be at least adox treating o separately; i thought there were more like inc/dec in the 'old-but-still-used' instruction space but maybe misremembering
@moonchild @harold bt/btc/similar modify CF, preserve ZF, and undefined other flags, so a valid implementation could preserve all but CF
@corsix @harold 'just as the works of shakespeare were written by an infinite number of monkeys, so too the x86 architecture...'
@moonchild @harold And then arm64 came along, with sane and tasteful flag behaviour, but the infinite monkeys wanted to efficiently emulate x86 on arm64, and so rmif was invented.
@harold ik there is some bullshit with unmodified flags that needs extra tracking, but there are a few cases where those turn up. and anything special wrt adc should also apply to o with adox?