A few of our SEMs have these external scan generators/frame grabbers that ~worked. All of the scans from the 35C before this year were captured on one (including this scan of an ICE40 FPGA).

Problem is they use a proprietary fiber-optic PCI card. The software is windows XP only and infuriating to use.

I traced out the PCB for the X/Y sweep DACs + buffer/offset circuits, then captured that in KiCad.

Seems like a great place to drop in an ICE40.

#Microscope #ElectronMicroscope #OpenHardware

The way they used the DAC is a not exactly standard, but it's just resistors and switches internally so you can kinda do whatever you want externally.

On the LTC7545 parallel DAC the Vref pin is used as an output, and the output pin used as Vref.

This was initially confusing when all knew was that high speed scan DAC output connected to a low speed serial DAC output.

The 7545 DACs have good max allowable voltages in a few key spots to make this as ok as it apparently is.

@nanographs Nice work ! I've recently been looking at my SEMs electronics, mostly to modernize them, and ran into the use of multiplying DACs all over the place. Do you know if there are any good modern replacements, preferably with serial interface?

@peterbjornx We're working on exactly this in long run. I have seen the serial DAC game played out in a few implementations and have never been happy with the results.

If you can't update everything in the microscope at the same rate that you do your scanning then there is at a minimum additional analog complexity needed to make alignment functions work properly.

I think this is why microscopes have tended to have a lot of board to board cables and extra control circuits for different modes.

@peterbjornx For the update rates we want to be able to hit to do ultra fast scan applications in TEM parallel DACs and FPGAs make a ton of sense.

Overkill for a lot of stuff but I think there's a simplicity in being able to largely use the same thing for everything.

@nanographs Hmm. I was indeed planning to roughly stick to the original analog design, where there are only slow DACs in the SEM, and tons of trimmers, which I also hope to replace with DACs.

For example, the column deflection signal path involves the analog scan fed through 10 bit MDAC for magnification set, then an 8 bit MDAC for energy compensation (Vlink) , then XY ortho control, analog offset and gain and finally the power amp.

@nanographs I guess its probably best to keep that, as the dynamic range needed to replace it all with one fast DAC and FPGA would be unfeasible. I do want to go from parallel buses everywhere to I2C for control, and replace the sweep gen with fast DACs.