VertigoDiscovered one problem with my circuit design -- for some reason, the MOSI signal on the FPGA is stuck high. Which means the flash ROM is never receving a command to read data.
THAT WOULD DO IT.
Directed MOSI and CLK signals out the PMOD port, and I confirmed my Verilog code *is* generating a proper signal. I can even see the DMAC address counter ... well, *count*. So that's cool!
And the signal quality on this FPGA board is total shite. It's amazing anything works at all.
That said, I now know for a fact that either the FPGA<-->CPLD link is malfunctioning, or the CPLD<-->flash link is malfunctioning.
It's clear that these parts *can* work, for the FPGA itself is programmed *through* these paths from the flash ROM. The question is, what magic incantation do *I* have to do to make this path work?
See folks, this is why you should never trust your simulations, even if they appear to work fine. ;)
Hopefully someone on the icoBoard support list can offer some help. Meanwhile I am going to try to find the source files to the CPLD on this board. If this board is as open source as they claim, they gotta publish the source code *somewhere*.
NIIICE!!
The problem was that I swapped the FPGA pins for MOSI and MISO. The schematic wasn't very clear about this.
HEY EE TYPES USING FPGAS -- NEVER EVER label your pins SPI_DO/SPI_DI or SPI_SO/SPI_SI. These are AMBIGUOUS LABELS and can mean anything depending on your master or slave POV.
ALWAYS BE EXPLICIT. MOSI or MISO ONLY.
Thank you.
I just confirmed that I am now able to get data from flash ROM. And, at the maximum speed possible, too -- 50 Mbps. Quite happy now!