Anuejn reported progress at this weeks IRC team meeting with reverse engineering the 5D Mark II image sensor, hardware (a 4 layer PCB) has been designed to interface between Z-turn Lite FPGA development board and the image sensor.
| AXIOM Beta | https://www.apertus.org/axiom-beta |
| Telegram group | https://t.me/apertus |
| Website | https://www.apertus.org/ |

















