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Quick primer on basic nMOS process steps. The piece traces the shift from bipolar and pMOS to nMOS dominance and then to CMOS for much lower static power. Key fabrication points are careful silicon substrate selection, LOCOS field isolation and the Kooi white ribbon issue, poly silicon gates that enable self aligned source and drain, and threshold tuning by ion implantation for enhancement and depletion devices. Full series at Florisera
Walk through CMOS fabrication from 3 µm to 1.25 µm in this friendly primer. It explains substrate selection crystal orientation twin well choices LOCOS isolation gate formation and why CMOS uses virtually no static power compared with NMOS. Practical details on mask costs layer thicknesses and early 1980s process steps make it useful for students and engineers wanting historical context before moving to smaller nodes. Read it on Florisera.
Quick explainer: CMOS scaling powered decades of faster and denser chips by shrinking MOSFET dimensions while keeping the same physics and leveraging silicon materials and improved fabrication. Dennard scaling showed how proportionate reduction of geometry and supply voltage keeps speed up and power down. But short channel effects and leakage emerge at nanometer scale. Below about 100 nm new device architectures become necessary. Read on Flo
Tourbillon watches are expensive but captivating. Invented by Abraham Louis Breguet to average out gravity related timing errors in pocket watches, the tourbillon mounts the escapement and balance wheel in a rotating cage. Today it is prized as kinetic art and a mark of craft more than a practical fix. If you're curious this article explains the history, how it works and some more affordable options.
Quick explainer on CMOS scaling in the microelectronics era 1 μm to 0.1 μm. Early submicron used quasi constant voltage scaling which thinned gate oxide and raised electric fields causing hot carrier and punch through problems. Fixes included APT implants, lightly doped drain spacers, p plus polysilicon gates, salicide contacts and rapid thermal anneal to activate dopants. Around 1995 voltage scaling began to keep fields manageable.
Scaling beyond 100nm - Nanoelectronics Era - Florisera: In this article, we explore the era of nanoelectronics, where device dimensions have scaled from 100 nm down to just a few nanometers. This continues our series on technology of integrated systems, which began with the f
https://florisera.com/scaling-beyond-100nm-nanoelectronics-era/
Semiconductor packaging shapes performance and reliability. It protects, powers, cools and electrically connects ICs while also introducing parasitic, thermal and EMC challenges. Key steps include wafer thinning, dicing and wire bonding such as ball bonding. Choosing interconnects means balancing cost, performance and reliability as chips and pin counts grow.
I mapped my 28 Vallejo Model Color paints into HSV space to find a more logical rack order for my 3 row by 16 column storage. The article includes an interactive 3D HSV plot, value histograms and KMeans clustering that reveal natural color groups and suggest one or two extra paints for balance.
Played with k means color quantization on Rembrandt's The Sampling Officials and on 10 other images to see if my set of 28 Vallejo Model Color paints covers palettes I like. With 30 clusters the algorithm picked mostly red and orange tones for Rembrandt and the recolored image lost many gradients and subtle tones. Combining images highlights real gaps in my palette and helps decide which paints to add.
Working on a pleasing and meaningful visual sort for my Vallejo paints. I compared three color extraction methods and two sorting approaches. PCA projects HSV into two dimensions for a simple interpretable layout. XGBRanker uses gradient boosting to learn a preferred ranking. Encycolorpedia swatches looked darker than my photo samples. Read the post for methods and code if you want to try this yourself.
https://florisera.com/sorting-vallejo-paints-with-machine-learning/
