So what can you do with the ability to read arbitrary #FPGA registers out of your design over #UART? Capture time series data (last four #ethernet packet bytes) in your regs and write a little #python script that launches #GTKWave and you have yourself a tiny homemade cross platform logic analyzer thing!
https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Debug-Probes