Reading "The Design of an Asynchronous MIPS R3000 Microprocessor" (https://www.researchgate.net/publication/2448388_The_Design_of_an_Asynchronous_MIPS_R3000_Microprocessor), a very different way to implement the classsic #RISC #pipeline
KW: #AsyncLogic #Architecture #processor
Fun! I wonder if Valve's Portal took inspiration from the Real World Potato computer (300 kHz @ 0.75 V) described in https://www.researchgate.net/publication/280493949_25_Years_Ago_The_First_Asynchronous_Microprocessor
KW: #AsyncLogic #VLSI