And the current routing status. Nine pages of schematics done. Three left to go.
I think that's enough routing for one day. This is the second page of instruction decoding. Here we have:
* HALT opcodes - there's three of them, &00, &01, &ff. I don't know why they felt the need for three. Those octal NANDs are one gate per chip which. But &ff would, otherwise, decode to LD (HL),(HL). Z80 peoples will be proud of that.
* Some branching stuff.
* Some general stuff.
* Shift and I/O stuff.
(I know those comments aren't helpful. I'm tired).
If you'd like to compare the Datapoint and Z80 instruction sets I have an article which does exactly that:
https://bread80.com/2022/07/09/comparing-datapoint-2200-8008-8080-and-z80-instruction-sets/
If my ordering for this seems a little random it's because I'm following Kicads page numbering of the schematics. But I'm skipping forward to the instruction register because it produces a tonne of control signals which trace across the board.
Instructions are grouped by bits 7 and 6 of the bytecode. Depending on the opcode bits 4,3,2 and 2,1,0 encode the destination and source registers respectively.
BTW if you look at the bits of the opcode which are encoding the flags and compare then to the equivalent Z80 opcodes you'll notice they're identical. There are, of course, a lot of similarities between the 2200 and it's great grandchild.
It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.
It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.
This part of the circuit uses OC gates to select whether a branch needs to be taken. Z35A and Z35D will output zero if the flag matches the if true/if false specified by IR5. In IR2 is high we have an unconditional branch and, in that case, Z2A always drives the signal low.
Examine the circuit and you'll notice it's actually functioning as an OR gate (but with inverted logic). Using a single resistor helps reduce the chip count.
Flags and branch control. This is a nice, easy to understand circuit. It starts with computing the zero, sign and parity flags. Since we have a 1-bit ALU the sign and parity flags are re-evaluated for each bit. Sign flag is just bit 7 of the result. Carry flag circuit is on another page.
IRn are raw bits of the opcode from the instruction register. A multiplexer IC uses IR3 and 4 select a flag to test. IR5 selects for condition true or condition false.
Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.
While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.
On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.
Bread80