Want to try simulating #ASIC logic gates with #kicad It’s never been easier thanks to​​​​​​ Aki Van Ness (https://chaos.social/@lethalbit)! Check the latest #yosyshq blog post here:

https://blog.yosyshq.com/p/sky130-kicad-spice/

After Hours Engineering:

Welcome to a new journey exploring Systems on a Chip (SoC)s. In the series I'll focus mainly on two--possibly 4 SBCs--from Lone Dynamic's Machdyne range of boards: Schoko, Eis and Konfekt (not shown in video), and possibly the BlackiceEdge.

https://youtu.be/KwU_U5LCJcc

#fpga, #YosysHQ, #SoC, #SystemVerilog, #Machdyne, #RISC-V
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After Hours Engineering, Episode 20 just posted! Final episode!

https://youtu.be/DnlRsO3_0Cw

Source code: https://github.com/wdevore/RangerRisc...

Description:
This is the "last" episode of the RISC-V series. In it we add a PLL and reintroduce interrupts via CSRs.
At the end I discuss future "potential" series that involve FPGAs.

Using the BlackiceEdge from #folknology

#fpga, #YosysHQ, #IceStorm, #RISC-V
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After Hours Engineering, Episode 19 just posted!

In this episode we FINALLY synthesize the RISC-V RangerRisc softcore CPU!

https://youtu.be/n80-B5BAXP8

Using the BlackiceEdge from #folknology

#fpga, #YosysHQ, #IceStorm, #RISC-V
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After Hours Engineering, Episode 18 just posted!

In this episode we learn about UART via simulating and synthesizing.

https://youtu.be/5uUvWfJpWrE

Using the BlackiceEdge from #folknology

#fpga, #YosysHQ, #IceStorm, #RISC-V
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After Hours Engineering, Episode 17 just posted!

In this episode we learn about SPI and synthesize a SPI Slave that pretends to be an MCP23S17 IO Expander and by that I mean a trivial pattern matcher.

https://youtu.be/0oNpulbLews

Using the BlackiceEdge from #folknology

#fpga, #YosysHQ, #IceStorm, #RISC-V
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