RT @phithetasigma: On Nvidiaās Vera CPU ā
First, letās revisit the CPU architecture (see attached image) and its bundled memory
The referenced SOCAMM is a data centre class modular form factor for LPDDR5X (not to be conflated as two different things)
Now, 1 LPDDR5X DRAM die = 9.6Gbps/bit (max). Assuming a 32-bit package, 1 LPDDR5X DRAM package = 9.6 x 32 = 307.2Gbps (~38GB/s) bandwidth
1 SOCAMM is constructed using four LPDDR5X DRAM packages. Total bandwidth per SOCAMM = 38 x 4 = ~154GB/s
The Vera CPU setup uses 8 SOCAMM (8-channel), and therefore has 8 x 154 = ~1.2TB/s of bandwidth
The 1.5TB refers to the capacity. Assuming 32 (8 x 4) LPDDR5X DRAM packages in 1 Vera CPU, this infers the use of 48GB DRAM packages (not 192GB), i.e., 32 x 48. This could be for thermal/power management reasons
In short, each Vera CPU set up = 8 SOCAMMs = 32 LPDDR5X DRAM packages = 1.5TB capacity (32 x 48GB) = up to 1.2TB/s of bandwidth
Second, on market opportunity
Nvidia guided visibility into ~$20B of CPU revenue this year. What is unknown is how this breaks down into sales configurations (and by extension, the memory modules/density types that may be required)
Possible configurations:
1 ā as part of Vera Rubin. Assuming NVL72 setup (72 Rubin GPUs, 36 Vera CPUs), total LPDDR5X memory capacity = ~55TB (36 x 8 x 4 x 48), which could potentially be higher if they use higher-capacity memory packages (with liquid cooling)
2 ā dedicated Vera CPU racks. Each rack packs 256 Vera CPUs, and therefore up to ~400TB of LPDDR5X memory (256 x 8 x 4 x 48), which could potentially be higher if they use higher-capacā¦
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https://x.com/phithetasigma/status/2057311668405944821#m