This week at embedded world 2026, join two ecosystem panels on how RISC-V is shaping the future of embedded innovation.
Hear insights from Siemens, Andes, Semidynamics, SiFive, Akeana, Nuclei, Synopsys, and DAMO Academy.
📍 Hall 5 Exhibitor Forum
⏰ Tue Mar 10, 10AM | Wed Mar 11, 3PM
☁️ Discover how AWS is powering a new era of processor design.
Join Jeremy Dahan at #RISCVSummit as he explores cloud-first hardware/software co-design and real-world RISC-V innovation.
🔗 Register: https://events.linuxfoundation.org/riscv-summit/program/schedule/
NASA, Google and more will join #RISCVSummit North America 2025, Oct 22–23 in Santa Clara.
Keynotes, workshops, and demos will showcase the future of open computing.
https://hubs.la/Q03Llm5B0
#RISCVEverywhere
🚀 NASA, Google Amongst Stellar Line-up for #RISCVSummit North America 2025 Join the global RISC-V community Oct 22–23 in Santa Clara for two days of keynotes, workshops, technical sessions, and an expo floor buzzing with demos. Hear from ecosystem leaders like Clayton Turner, Daniela Barbosa, Martin Dixon, Krste Asanovic, and Ted Speers. 💡 Why attend? - Face-to-face collaboration accelerates ideas. - Inspiration flows from live demos and thought leaders. - Stronger connections with innovators across the ecosystem. New to RISC-V? Start with RISC-V 101 on Oct 21 for a solid foundation before the Summit. Looking to sharpen your skills? Join the hands-on Developer Workshops on Oct 22 and learn to design, verify, and optimize RISC-V hardware & software. From AI to HPC, Security to Software, there’s a track for everyone. Don’t just read about it—shape the future of open computing in person. NASA - National Aeronautics and Space Administration, Google, SiFive, Microchip Technology Inc. #RISCVSummit #RISCVEverywhere
We're in Paris for RISC-V Summit Europe! Visit our poster exhibition at Island 2.1 (Level -2) and learn more about Codethink's work on RISC-V. 👋
Tomorrow, the team will present ‘Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions’ at 12:45 p.m., Gaston Berger (S2). Find out more here: https://www.codethink.co.uk/articles/risc-v-summit-europe-2025-preview/
RISC-V Summit Europe gets underway in Paris today! In our blog post, find out where and when you can find us, including:
- Details about our talk, ‘Implementing Runtime-Configurable Endianness in RISC-V: Challenges and Solutions’
- Where and when you can chat to our engineers at our poster exhibition
- How to arrange a meeting with the team to learn more about our work on RISC-V
→ What to Expect from Codethink at RISC-V Summit Europe 2025: https://www.codethink.co.uk/articles/risc-v-summit-europe-2025-preview/
RISC-V Summit Europe is just around the corner (12-15th May), and Codethink will be attending
In Paris, we'll be presenting our recent work on big-endian support for RISC-V. This internal project involved patching QEMU and other open source software to enable big-endian operation (without existing hardware support!).
Sound interesting? Read our blog post on the project: https://www.codethink.co.uk/articles/risc-v-big-endian-support-runtime-testing/
See you in Paris!
#RISCV #RISCVEverywhere #RISCVSummitEurope #opensource #qemu
A Microchip adotou o Risc V e lançou um microcprocessador de 64 bits
Microchip PIC64GX is a quad-core 64-bit RISC-V microprocessor for real-time processing
As the dust settles following RISC-V Summit Europe, we've had some time to reflect on our time in Munich.
We always enjoy our work with the RISC-V community, from the engaging talks and speakers we listened to and learned from, to the delegates we spoke to at our poster presentation.
Read our round-up of RISC-V Summit Europe here, including a summary of our presentation: https://buff.ly/3zjvDyQ
RISC-V
The demand for RISC-V expertise is soaring - stand out in the crowd. Get certified, showcase your skills and advance your career! Find out more here: https://hubs.la/Q02pD1W20
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